This Non-provisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 093103814 filed in Taiwan on Feb. 17, 2004, the entire contents of which are hereby incorporated by reference.
1. Field of Invention
The present invention relates to a construction of strain-relaxed SiGe layers and method for fabricating the same, and more particularly to a construction of thin strain-relaxed SiGe layers and method for fabricating the same for strained Si using SixC1-x as insert layers.
2. Related Art
The semiconductor and integrated circuit technology has been developed in recent years, to be compact with high operation speed. How to increase the operation speed of the semiconductor device with lower power consumption constitutes an important issue in the very large scale integration (VLSI) field.
Researches on SiGe material have shown that when a composite layer of Si and Ge is grown on a silicon substrate and followed with a strained Si layer, a two-dimensional porous layer of electrons and holes is formed at the interface between the relaxed SiGe layer and the strained silicon channel, which increases electron drift mobility in a channel of the semiconductor device and, consequently, the semiconductor device performance.
In the conventional SiGe epitaxial technology, the strain-relaxed SiGe epitaxial layer is formed on the Si substrate, and a strained Si layer is then formed on the epitaxial layer. The subsequent structure is employed as a “virtual substrate” for replacing the original Si substrate, and may be applied to an integrated process of the Si substrate and the transistors with high carrier mobility, MOS transistors, or III–V family semiconductors. These strain-relaxed SiGe epitaxial layers need the characteristics of high strain-relax, smooth surface, and relatively low density of threading dislocations.
The conventional SiGe epitaxial growth technology, for example, the compositionally grated buffer, takes long time and induces the increasing roughness on the surface of the epitaxial layer. The characteristic of the elements may be destroyed.
The prior art disclosed some solutions regarding the SiGe epitaxy growth technology. U.S. Pat. No. 6,291,321 provides a graded SiGe buffer for the growth of the stain-relaxed SiGe epitaxial layer, which is the main technology trend. However, growth of the epitaxial with thickness takes longer time and leads to difficult alignment of the lithography process.
Besides, U.S. Pat. No. 5,221,413 provides a SiGe hetro-structure graded epitaxial layer with low dislocation formed in high temperature. However, the 413 patent does not provide any other structure regarding the dielectric layer. Furthermore, the high temperature affects the uniformity of the SiGe layer.
In the application of CMOS high speed components and optical and electronic components, the performance of the devices may be enhanced through replacing Si substrates with strain-relaxed SiGe layers. For the foregoing reasons, there is a need for highly strain-relaxed SiGe layers with low threading dislocations density, having the same relaxation of SiGe, and reducing thickness of SiGe layers.